1. Field of the Invention
The present invention relates to computer architecture and digital systems. More particularly, the present invention relates to a means for collecting boolean conditions of multiple operations in a microprocessor.
2. Description of Related Art
It is useful in certain applications to be able to perform a series of computer operations, be they boolean, logical, or arithmetic, and to produce a single word containing a number of bits, each bit representing a boolean result for one of the operations performed. An example of this resides in a common graphics two-dimensional window clipping. In such a clipping, the final boolean result--TRUE or FALSE--refers to whether a point on a plane lies inside a rectangular region bounded by cartesian coordinates (X.sub.1, Y.sub.1) (X.sub.2, Y.sub.1), (X.sub.1, Y.sub.2) and (X.sub.2, Y.sub.2). Whether the point resides in such a region may be determined by determining whether the X coordinate of the point is less than X.sub.1, whether the X coordinate of the point is greater than X.sub.2, whether the Y coordinate of the point is less than Y.sub.1, and whether the Y coordinate of the point is greater than Y.sub.2. The results of these four determinations can be used to construct a four-bit word embodying TRUE (the relevant coordinate is less or greater as asked) or FALSE (the relevant coordinate is not less or greater as asked). Of course, four FALSE's means the point does lie in the rectangular region. Assuming TRUE's and FALSE's can take on values 1 and 0, respectively, the result of each operation can be placed into a four-bit word that will be zero if the point is in the rectangular region, and non-zero otherwise.
Heretofore, collection of conditions as described above has been handled two different ways. One way involves condition collection by software. In this technique, several simple computer operations are used to generate an operation result, to reduce this result to a single bit indicating whether the result is TRUE or FALSE, and then to shift or to rotate this bit into a multi-bit word containing other conditions. In some embodiments of this type of condition collecting, several steps are combined. However, in all cases two or more operations are required to process each condition collected. Thus, this manner of condition collecting is generally inefficient.
The second prior art way of collecting conditions involves hardware. In this technique, a special computer instruction is created, and special computer hardware added, to allow conditions to be collected, but with constraints on just which operations can contribute to the collection. An example of this is the 34010 graphics processor manufactured by Texas Instruments Incorporated of Dallas, Tex. This processor contains a special window clipping operation that performs multiple comparisons, and that places the comparison results in a special register. Shortcomings of this approach are that the instruction set of the processor must be modified and that a programmer cannot readily specify arbitrary conditions to be collected.
Based on the foregoing, it is clear that it is a shortcoming and deficiency of the prior art that there is nowhere disclosed or suggested an apparatus or method lacking multiple software operations per conditions collected, allowing collection of a series of conditions produced by operations of arbitrary type, and obviating need for a change to the instruction set of a processor to which it may be added.
Although there are no known prior art teachings of a solution to the aforementioned deficiency and shortcoming such as that disclosed and claimed herein, a number of prior art references exist that discuss subject matter that bears some relation to matters discussed herein. Such prior art references are U.S. Pat. Nos. 4,212,076, 3,982,229 and 4,525,776. Each of these references is discussed briefly below.
U.S. Pat. No. 4,212,076 to Conners is directed to a digital computer structure in which boolean logic operations control arithmetic logic operations. Conners' digital computer structure performs chained boolean logic processing on any selected bit of various selected words held in memory. Then, Conners' structure uses the logic processing result by storing it at any selected bit location in any of various selected words held in memory.
U.S. Pat. No. 3,982,229 to Rouse et al. relates to a combinational logic arrangement. Rouse et al. disclose such an arrangement for use in a data processor that selectively performs a plurality of bit manipulations or logic operations including shift, rotate and insert under mask. Rouse et al.'s arrangement is controlled by a single instruction format which specifies the parameters needed for each of the operations.
U.S. Pat. No. 4,525,776 to Eldumiati et al. teaches an arithmetic logic unit that moves, in response to instructions residing in an instruction register, any bit from any position in a source to any bit position in a destination in a single instruction interval.
Review of each of the foregoing patents reveals no disclosure or suggestion of a system or method such as that described and claimed herein.